entity iob_loc_ex is port (CLK : in STD_LOGIC; A, B : in STD_LOGIC_VECTOR (3 downto 0); O : out STD_LOGIC_VECTOR (3 downto 0));
attribute xc_loc : string; attribute xc_loc of CLK : signal is "P13"; attribute xc_loc of A : signal is "P19,P20,P23,P24"; attribute xc_loc of B : signal is "P25,P26,P27,P28"; attribute xc_loc of O : signal is "P48,P49,P50,P51"; end iob_loc_ex;
architecture xilinx of iob_loc_ex is
signal Q : STD_LOGIC_VECTOR (3 downto 0);
begin U0: process (CLK) begin if (CLK'event and CLK='1') then Q <= A; end if; end process;
-- Insert user's application here O <= Q and B;
end xilinx;
3
I/O ロケーションを HDL に割り当てる (Verilor コード)
module iob_loc_ex (CLK, A, B, O); input CLK /* synthesis xc_loc="P13" */; input [3:0] A /* synthesis xc_loc="P19,P20,P23,P24" */; input [3:0] B /* synthesis xc_loc="P25,P26,P27,P28" */; output [3:0] O /* synthesis xc_loc="P48,P49,P50,P51" */;