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AR# 2432

2.1i NGD2VER: What is needed to do Verilog simulation of 3rd party designs using Xilinx Alliance software?

説明

Keywords: ngd2ver, Verilog, simulation

Urgency: standard

General Description:
What is needed to do Verilog simulation of 3rd party designs in the
Xilinx Alliance software?

ソリューション

A generic Verilog HDL interface is supplied with the Xilinx Alliance software,
consisting of the NGD2VER netlister, and generic SIMPRIM-based and
UNISIM-based Verilog simulation libraries.

Simulation libraries are used at 4 stages of the FPGA implementation flow:
RTL (UNISIM), post-NGDBUILD (SIMPRIM), post-Map Timing (SIMPRIM),
and post Route Timing (SIMPRIM). Please see (Xilinx Solution 2703) for
details.

For the CPLD flow, supports simuilation at 3 points: RTL (UNISIMS),
post-NGDBUILD (SIMPRIM) and post-fitting timing (SIMPRIM).

Please see (Xilinx Solution 3167) on details of using Verilog-XL with the
Xilinx Alliance software to point to the SIMPRIM-based libraries.
AR# 2432
作成日 08/31/2007
最終更新日 07/31/2001
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