AR# 2446


FPGA Configuration: Async Periph mode, RDY/BSY state when DONE is held low.


General Description:

When configuring a device through Asynchronous Peripheral mode,

is the RDY/BSY pin still active when the DONE pin is held low

to stall startup and operation?


The RDY/BSY pin is active until the I/O's are released. With

the default makebits or bitgen options, the I/O's are released

after the DONE pin is released. So if the DONE pin is held low

(and SyncToDone is enabled, see comments below) then the

RDY/BSY pin will still be active.

However, the RDY/BSY pin will not indicate BSY (BSY = 0) just

because the DONE pin is being help low. The RDY/BSY pin will

only indicate BSY if the FPGA is serializing the data on the 8

bit data bus for configuration. If the DONE is held low, but

no data is being written to the bus, then RDY/BSY will indicate



The holding the DONE pin low can stall startup and operation

only if the SyncToDone option is enabled in makebits or bitgen.

If SyncToDone is not set then the FPGA will not monitor the

external state of the DONE pin, it will release the DONE pin at

the end of configuration and proceed with startup whether the

DONE pin is externally held low or not.

AR# 2446
日付 05/08/2014
ステータス アーカイブ
種類 一般
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