General Description: To perform timing or post-synthesis functional HDL simulation in M1, the Verilog and/or VHDL (VITAL) SimPrim models must be compiled for use in QuickHDL. If instantiated LogiBLOX and/or Unified library components are to be behaviorally simulated, the LogiBLOX and/or UniSim libraries must be compiled, as well.
M1 includes the following scripts that automatically compile the Verilog and VHDL simulation models for your particular version of QuickHDL:
For more information on using these scripts, see the accompanying README files. These scripts should be run by your system administrator.
NOTE: The Verilog compile script will only compile XC3000, XC4000X (not XC4000E), and XC5200 UniSim models (M1.4 and later only). To compile the UniSim libraries for other device families, see Part 2 of this Answer Record.
The information below is intended primarily for reference. As compile scripts for QuickHDL are included with the Mentor Graphics interface, you should not need the following instructions unless you wish to compile UniSim libraries for families not listed in the Verilog compile script (e.g., XC4000E or XC9500), have problems with the compile scripts, or need to perform a partial library compilation.
M1 contains three types of HDL simulation libraries, and CORE Generator contains one:
SimPrim - Library of generic simulation primitives LogiBLOX - Library of LogiBLOX simulation models UniSim - Library of Unified component simulation models (A1.4+) XUL - COREGen VHDL Library containing some arithmetic functions
The instructions that follow refer to the following variables:
VERILOG_DESTN - Location for compiled Verilog libraries Recommended setting: $XILINX/mentor/data/verilog
VHDL_DESTN - Location for compiled VHDL libraries Recommended setting: $XILINX/mentor/data/vhdl
If you want logical library names to be available for all designs, set your QUICKHDL environment variable to the location of your master quickhdl.ini file:
For example: setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini
If QUICKHDL is not set when qhmap is run, the logical library mapping is done locally; therefore, all qhmap commands would have to be run for each new HDL design.
For Verilog users, the compilation commands that need to be executed are: