The question often arises as to how you can constrain your I/O to specific pad locations in a Synopsys synthesis flow.
There is actually no support for adding attributes directly to components in a VHDL or Verilog netlist, however, I/O location constraints can be added using one of the following techniques instead:
- adding constraints from a Synopsys compile script - adding constraints to a .ucf file (for M1) constraint - adding constraints to a .cst file (for XACT)
- adding constraints via the Xilinx Constraints Editor (A1.5 and later)
ソリューション
1
From you Synopsys compile script, you may use the following command before writing out the implementation netlist:
This is detailed in the XSI User/Interface guide, pg5-15.
You may also use a .cst file (for XACT) or a .ucf file (for M1) constraint instead. Details on the syntax for these may be found in the Xilinx Libraries Guide for the repective tool.
2
There is actually no support for adding attributes directly to components in a Verilog netlist, however, I/O location constraints can be added using one of the following techniques instead:
- adding constraints to a .cst file (for XACT) - adding constraints to a .ucf file (for M1) constraint