In HDL Analyst, the output signal name (in the example, "a" is the instance name and "dout [3:0]" is the output signal name) will become the instance name of the RAM.
Synplify generates a warning message when inferring these RAMs. The message gives information about the RAM instance and contains the phrase, "Removing sequential instance <instance_name> view:<view_name> because there are no references to its outputs." You can safely ignore this warning.
The following are limitations of inferring Block selectRAMs:
* ENA/ENB pins currently inaccessible [always tied to "1"] * RSTA/RSTB pins currently inaccessible [always inactive] * Automatic inference not yet supported, syn_ramstyle attribute required for inferring Block RAMs * Dual port with Read-Write on a port not supported * Initialzing inferred RAM in the HDL code is currently not supported. To do this, you need to find out the instance name of the RAM from Synplify Technology View or from the EDIF netlist and apply INIT attribute in the UCF file. The inferred RAMs are initialized to '0' (zero) by default.
The designer has the option of instantiating the RAMB** cells to which these limitations are overcomed. Please see (Xilinx Solution 2022)
-- VHDL example -- Tested in Synplify 5.2.2a
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity ram_example1 is generic(data_width: integer:= 8; address_width:integer := 8; mem_depth: integer:= 256); port (data: in std_logic_vector(data_width-1 downto 0); address: in std_logic_vector(address_width-1 downto 0); we, clk: in std_logic; q: out std_logic_vector(data_width-1 downto 0)); end ram_example1; architecture rtl of ram_example1 is type mem_array is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0); signal mem: mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of mem : signal is "block_ram"; signal raddress : std_logic_vector(address_width-1 downto 0); begin l0: process (clk) begin if (clk = '1' and clk'event) then raddress <= address; if (we = '1') then mem(CONV_INTEGER(address)) <= data; end if; end if; end process;