説明

I have modified the BSPs generated in EDK 9.1i, and they compile in Windriver Workbench without errors. On downloading this image to the FPGA, there is no output on the serial terminal although it appears that the program is running fine. Why does this happen?

ソリューション

The BSP generated with UART Lite driver version 1.02.a does not have the SIO adapter information.  

To work around this issue, use UART Lite driver version 1.01.a instead of 1.02.a. 

This problem has been fixed in the latest EDK 9.1i Service Pack, available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.1i Service Pack 2.