AR# 25185

説明

The plb_ddr2_v1_01_a in Asynch mode is generating timing errors on signals, as in the following example: 

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Timing constraint: TS_dcm_1_dcm_1_CLK0_BUF = PERIOD TIMEGRP "dcm_1_dcm_1_CLK0_BUF" 

TS_dcm_0_dcm_0_CLKFX_BUF HIGH 50%; 

5099 items analyzed, 3 timing errors detected. (3 setup errors, 0 hold errors) 

Minimum period is 9.279ns. 

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Slack: -0.593ns (requirement - (data path - clock path skew + uncertainty)) 

Source: ddr2_sdram/ddr2_sdram/WO_ECC.DDR_CTRL_I/INITSM_I/Calib_start (FF) 

Destination: ddr2_sdram/ddr2_sdram/WO_ECC.DDR_CTRL_I/WO_ECC.WO_ECC_ASYNC.REG_UNREG_I/calib_rd_ctrl_d1 (FF) 

Requirement: 2.500ns 

Data Path Delay: 2.729ns (Levels of Logic = 1) 

Clock Path Skew: -0.112ns 

Source Clock: Clk_100MHz rising at 20.000ns 

Destination Clock: Clk_133MHz rising at 22.500ns 

Clock Uncertainty: 0.252ns

ソリューション

This problem has been fixed for the plb_ddr2_v1_02_b in the latest EDK 9.2i, available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
 

However, with respect to plb_ddr2_v1_01_a, add the following TIGs or constraints to the following paths: 

NET "ddr2_cal_clk" TNM = cal_clk_grp; 

NET "clk_133mhz" TNM = clk_133_grp; 

NET "sys_clk_s" TNM = clk_plb_grp; 

TIMESPEC TS_TIG0 = FROM cal_clk_grp TO clk_133_grp 7500ps; 

TIMESPEC TS_TIG1 = FROM clk_133_grp TO cal_clk_grp 20000ps; 

TIMESPEC TS_TIG2 = FROM cal_clk_grp TO clk_plb_grp 10000ps; 

TIMESPEC TS_TIG3 = FROM clk_plb_grp TO cal_clk_grp 20000ps; 

TIMESPEC TS_TIG4 = FROM clk_133_grp TO clk_plb_grp 10000ps; 

TIMESPEC TS_TIG5 = FROM clk_plb_grp TO clk_133_grp 7500ps;