AR# 2536


M1.2, Workview Office: EDIFNETI reports unconnected ports reading TIME_SIM.EDN


Keywords: EDIF, EDN, hierarchy, viewlogic, timing simulation

Urgency: HOT

To perform a timing simulation with Workview Office, a file called TIME_SIM.EDN
can be created from the M1 Design Manager. This EDIF file must be read back
into the Viewlogic environment using a program called EDIFNETI. The following
warnings may appear while reading the TIME_SIM.EDN file:

<<<WARNING>>> - Unconnected port I2 in cell XBA1
<<<WARNING>>> - Unconnected port I3 in cell XBA1
<<<WARNING>>> - Unconnected port I0 in cell XBA2
<<<WARNING>>> - Unconnected port COUT in cell XBA3
<<<WARNING>>> - Unconnected port D0 in cell XBA3
<<<WARNING>>> - Unconnected port F1 in cell XBA3

These XBA## files are levels of hierarchy that describe the design on the
logic level. The XBA## names are used to prevent overwriting the original
WIR files when the timing simulation netlist is read in. They are required to
perform a hierarchical gate-level simulation.

This behaviour is only seen with Workview Office 7.3 and newer with M1.2 only.



One way to avoid these warnings is to create a flattened EDIF file to be used
for the timing simulation. Run the following command in DOS from your project

ngd2edif -n -v viewlog <design>.ngd time_sim.edn

where <design> is the name of your top-level design, and time_sim.edn can be
changed to allow both flattened and hierarchical EDIF files to co-exist.
The -n option produces the flattened netlist.

The drawback of this solution is that you will not have complete
back-annotation to your schematic. Nets that descend into the hierarchy will
have unknown values on the lower levels. Again, this will not affect the
overall simulation results, but can impair your ability to debug the


The "Unconnected port" warnings are valid but harmless. The XBA files
describe the logic at different levels, from the function generators to
CLB logic to the logic block itself. These files are generically built with
all the possible pins, then the logic from the placed and routed design is
added. Because each component does not use all the possible resources, some
pins will be left unconnected.

For example:
Let's say that XBA1 described an F function generator containing a three-input
AND gate. This function generator has four inputs and one output, so pins
I0, I1, I2, and O will be used. However, pin I3 will be left unused, so
EDIFNETO will produce the warning for XBA1.

The warnings can be safely ignored because they have no effect on the
simulation. This issue has been fixed with M1.3.
AR# 2536
日付 03/27/2000
ステータス アーカイブ
種類 一般
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