AR# 2591: Foundation XVHDL, F1.3/F1.4: Bidirectional pins must be described in top-level entity
Foundation XVHDL, F1.3/F1.4: Bidirectional pins must be described in top-level entity
Keywords: VHDL, Metamor, bidirectional
Due to the hierarchical nature of EDIF and the way in which Metamor compiles hierarchical VHDL designs, bidirectional I/O must be fully described in the top-level entity to avoid illegal connections being made at the boundary of the top-level entity and the lower-level macros.
For bidirectional pins, the top-level entity should have the port declared as 'inout', and the 3-state function of the output should be described in the top-level entity. The lower-level entity should therefore have 2 ports, one for the input side of the bidi pin ('in'), and one for the output side of the bidi pin ('out'). Additionally, the 3-state enable signal may also now be an output port of the lower-level macro, since the output 3-state functionality is now described in the top-level entity.