We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2593

Foundation XVHDL, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers


Keywords: ngdbuild, xvhdl, bidirectional pins

Urgency: Standard

General Description:

NGDBUILD may give error,
"ERROR: basnu - logical net "net_name_int" has both active and
tristate drivers"
"ERROR: basnu - logical net "net_name_int" has multiple

when designing bidirectional I/O pins with hierarchical VHDL in


Due to the hierarchical nature of EDIF and the way in which
Metamor compiles hierarchical VHDL designs, bidirectional I/O
must be fully described in the top-level entity to avoid
illegal connections being made at the boundary of the top-level
entity and the lower-level macros.

For bidirectional pins, the top-level entity should
have the port declared as 'inout', and the 3-state function of
the output should be described in the top-level entity. The
lower-level entity should therefore have 2 ports, one for the
input side of the bidi pin ('in'), and one for the output side
of the bidi pin ('out'). Additionally, the 3-state enable
signal may also now be an output port of the lower-level macro,
since the output 3-state functionality is now described in the
top-level entity.
AR# 2593
日付 01/02/2000
ステータス アーカイブ
タイプ 一般