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AR# 2606

Foundation XVHDL F1.3/F1.4: VHDL compiler synthesizes design twice

説明

Keywords: XVHDL, Logiblox

Urgency: Standard

General Description:

The XVHDL compiler will run the synthesis of the design twice
if Logiblox are inferred.

ソリューション

If Logiblox modules are inferred by the XVHDL compiler, the
synthesis compiler will run twice -- once to generate a .EDN
EDIF file for implementation, and once to generate a .EDF EDIF
file, without Logiblox, for functional simulation.

The only way to force it to compile just once is to disable the
Logiblox inference by deselecting the Logiblox option in the
Synthesis -> Options dialog of the HDL Editor.

Logiblox inference may be disabled when doing multiple
iterations of functional simulation, to reduce runtime of the
synthesizer. However, it is recommended that when going into
the Design Implementation portion of the flow, the Logiblox
inference switch is enabled to provide optimal results and
performance in the design.
AR# 2606
作成日 07/29/1997
最終更新日 01/02/2000
ステータス アーカイブ
タイプ 一般