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AR# 2621

Foundation State Editor: E:#002 Syntax error near "<="


Keywords: vhdl fsm case diagram action
Urgency: Standard

General Description:
When synthesizing a finite state machine (FSM) using the
Foundation State Editor, the following error occurs:

E:#002 Syntax error near "<=".


This will happen if you have a Diagram Action in your FSM
that contains a CASE statement, or any statement that uses
the => operator.

The State Editor changes the statement from:

case (inputs) is
when "000" => outputs <= "101";
... ^^

to an incorrect syntax:

case (inputs) is
when "000" <= > outputs <= "101";
... ^^^^

The workaround is:

1. In the State Editor, select Synthesis->HDL Code
Generation. Click Yes to view the HDL code.

2. In the HDL Editor, select Edit->Read Only to turn off
the read-only mode.

3. Correct the CASE statement syntax.

4. In the HDL Editor, select Synthesis->Synthesize. When
synthesis is complete, exit the HDL Editor.

If your FSM is your top-level design, skip step 5.

5. In the State Editor, select Project->Create Macro or
Project->Update Macro to create or update the library
AR# 2621
日付 04/06/2000
ステータス アーカイブ
タイプ 一般