library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity tenths_ex is port ( clkint, clkenable : in STD_LOGIC; xcountout : out STD_LOGIC_VECTOR(9 downto 0)); end tenths_ex;
architecture xilinx of tenths_ex is
attribute syn_black_box : boolean;
component tenths port ( CLOCK : in STD_LOGIC; CLK_EN : in STD_LOGIC; Q_OUT : out STD_LOGIC_VECTOR(9 downto 0)); end component; attribute syn_black_box of tenths : component is true;