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AR# 2715

PEARL: Support for Cadence's Affirma Pearl Timing Analyzer?


Keywords: Pearl, static timing

Urgency: standard

General Description:
Is there support for Cadence's Affirma Pearl Timing analyzer?

For info on Pearl:


At this time, Xilinx can only recommend Trace until Cadence
demonstrates a flow that matches TRCE results. For 2.1,
Xilinx is looking into supporting some third party static analysis
tools including Quad-Motive Blast, Primetime, etc., however,
there is no plans to support the static analysis capabilities of

The simulation netlist provided is intended for simulation only
and does not work so well for static analysis since it is written
in terms of gates rather than FPGA architectural components.
The simulation libraries have wire delays which are included
with each component in the netlist so every FF and every
gate could have a different delay associated with it. Even if
this is not the case, a library would need to be created for
every device-speed grade combination. For the little added
benefit the Pearl static analysis tools would provide, it does
not seem worth it. The numbers are not going to be accurate
until the design is run through PAR. For now, Timing Analyzer
is the static analysis tool.

To support Pearl, Xilinx will need to generate TLF files for Pearl.
TLF is Cadence's Timing Library Format. It is an ASCII format
file representing timing parameters associated with any cell in a
particular IC process technology.
AR# 2715
日付 06/13/2002
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