We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2732

CPLD XC9500 Family Hitop - How to control Timing in a CPLD


Keywords: timing, timespecs, timing optimization, local

Urgency: standard

General Description:

Improving timing of your CPLD design



Global Timing Optimization:

By default, the fitter performs global timing optimization on
logic paths in your design. Timing optimization will shorten
your critical paths as much as it can. In general, timing
optimization optimizes logic and allocates the fastest
available resources for the longest paths in your design,
assuming all paths are equally critical. In some cases, the
fitter trades off density for a speed advantage.

Global Timing Optimization is user controllable from the
implementation options template.


Collapsing Pterm Limit:

If you find that the path delay of a larger, multi-level logic
function is not satisfactory, try increasing the p-term limit
parameter to allow the larger functions to be flattened
further. For example, you may try increasing the p-term limit
to 50 when rerunning the fitter.

The allowable limits for XC9500/XL designs are between 2 and 90.


Using Timing Specifications:

You can enter Timing Specifications for your design through
either your schematic or a UCF file.

The following path types can be controlled using timing

Pad-to-pad delay Input port to an output port

Register setup time Input port to the data pin of a
flip-flop, including flip-flop setup

Register-to-register Clock pin of a flip-flop to the data
pin of the same or different
flip-flop, including flip-flop setup

Clock-to-output delay Clock pin of a flip-flop to an output

For a more detailed description of how to use Timing
Specifications, please refer to the Libraries Guide available
online at:
Click on the Manuals appropriate for your software version.


Reducing Levels of Logic:

The XC9500 architecture, like most CPLD devices, is organized
as a large, variable-sized combinational logic resource
(the AND-array and XOR gate) followed by a register. If you
place combinational logic before a register in your design, the
fitter maps the logic and register into the same macrocell. The
output of the register is then directly available at an output
pin of the device. If, however, you place logic between the
output of a register and the device output pin, a separate
macrocell must used to perform the logic, decreasing both the
speed and density of your design.


Using Local Feedbacks:

By default, all internal nodes in an XC9500/XL design (those that
remain after collapsing) are routed via the FastCONNECT
structure. There are also higher-speed routing paths that feed
back from each macrocell to the inputs of the same local
function block. To use the local feedback path for a particular
node in your design, both the source logic and the load logic
on the node must be explicitly mapped to the same function
block. You must apply the following two constraints:

1. Constrain both the driving function and load function(s) to
the same function block using the LOC=FBnn attribute.

2. Apply a timing specification to the path that would require
the local feedback path (so that the path cannot be satisfied
using FastCONNECT routing delays).

Hint: You can specify the value of 1 ns in your timespec to
tell the fitter to use local feedback, even though the fitter
will warn you that it cannot satisfy your timespecs.

As an alternative to applying a timing specification (#2), you
can turn on the Use Local Feedback option in the Design
Manager. But, that would allow the local feedback path to be
used for any other internal nodes in the design that run
between two functions that happen to get mapped to the same
function block.
AR# 2732
作成日 08/28/1997
最終更新日 06/13/2002
ステータス アーカイブ
タイプ 一般