We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2746

Foundation XVHDL: Synthesis error "Wrong number of fields bus on line #__ in .xas file"


Keywords: Metamor, VHDL, Wrong, fields, bus, xas

Urgency: Standard

General Description:
Using Foundation XVHDL to synthesize the code, the following
error is reported:
"Wrong number of fields bus on line #__ in .xas file"


A possible cause of this error is that in the VHDL code a
single bit was specified as a vector as shown below:

sig_name: out std_logic_vector(7 downto 7);

The solution is to change this to a single bit such as:

sig_name7: out std_logic;
AR# 2746
作成日 09/02/1997
最終更新日 01/02/2000
ステータス アーカイブ
タイプ 一般