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General Description: The symptom is that some properties attached to Concept schematics (typically properties attached to the TIMESPEC and CONFIG symbols) do not get written out by Concept2XIL to the output EDIF file.
Concept has a feature called "HDL Direct", which allows it to directly write out a Verilog netlist for every schematic block in your design. Since the Verilog netlist format does not support properties, HDL Direct also writes out a separate viewprps.prp file containing the properties associated with the instances in a design block, and it does this for each design block.
In this bug, the properties do get written out by HDL Direct to the viewprps.prp file for the design block, but do not appear in the final EDIF output file.
This problem is caused by a bug in HDL Direct in the Cadence 97A release.
The problem is that the instance names HDL Direct writes to the Verilog file for the design block are mixed case:
Example: obuf16 \Page1$6p
while HDL Direct writes these same instance names out in lower-case in the viewprps.prp file:
Example: Block "page1" Inst "\\6p\\")
A typical symptom will be messages in your concept2xil.log file that look like:
Instance page1$6p in property file for ftope_lib.ftope:hdl does not exist in design
This is a message from the Cadence EDB, saying that it has found a property in the viewprps.prp file which it can't correlate with anything in the Verilog file.
There is a hot fix available from the Cadence FTP server to correct this problem. The first patch to fix this problem was called conceptHdldr03.01-s001 and was located in: