AR# 2780: 1.3 XC9500 Hitop - Logic erroneously trimmed away when using HDL macros in 9k schematic design
AR# 2780
1.3 XC9500 Hitop - Logic erroneously trimmed away when using HDL macros in 9k schematic design
説明
Keywords: 9500, CPLD, trim, VHDL
Urgency: Standard
General Description:
This problem occurs when an HDL macro drives 2 or more of its output pins from the same net. The problem has been confirmed with Metamor and Exemplar netlists; Synopsys DC netlists avoid this problem. Symptom is that all logic in the schematic sourced by all but one of the duplicate macro pins is trimmed from the design. That is, only one of the commonly-sourced macro pins will remain connected; which one is arbitrary.
For example, the following problematic HDL macro produces 2 outputs driven by the same net (only one flop is inferred):
entity afd is port (din: in STD_LOGIC; clk : in STD_LOGIC; dout1, dout2 : out STD_LOGIC); end afd; architecture afd_arch of afd is begin process (CLK) begin if CLK'event and CLK='1' then DOUT1 <= DIN; DOUT2 <= DIN; end if; end process; end afd_arch;
ソリューション
This issue has been fixed for M1.4.
For M1.3, a possible workaround for Foundation XVHDL (Metamor) is to create an internal intermediate signal for each commonly-driven output port, and assign the Metamor "critical" attribute to each signal, as follows:
library METAMOR; use METAMOR.attributes.all; entity afd is port (din: in STD_LOGIC; clk : in STD_LOGIC; dout1, dout2 : out STD_LOGIC); end afd; architecture afd_arch of afd is signal q1, q2 : STD_LOGIC; attribute critical of q1 : signal is true; attribute critical of q2 : signal is true; begin process (CLK) begin if CLK'event and CLK='1' then q1 <= DIN; q2 <= DIN; end if; end process; DOUT1<=q1; DOUT2<=q2; end afd_arch;