The BSCAN component indicates that boundary scan logic should be enabled after the programmable logic device (PLD) configuration is complete. It also provides optional access to some special features of the XC5200 boundary scan logic. To indicate that BSCAN should remain enabled after configuration, connect the BSCAN component to the TDI, TMS, TCK, and TDO pins.
For Virtex and Spartan-II, the JTAG ports are dedicated and always available. The BSCAN symbol is not needed for basic JTAG functions, or for multiple Boundary Scan operations.
For advanced JTAG users, BSCAN_VIRTEX/BSCAN_SPARTAN2 is available to access and control the user registers created with Boundary Scan TAP controller.
You can instantiate a BSCAN cell by using the Xilinx family library supplied with Synplify. Please see (Xilinx Solution 244) for details on instantiating Xilinx-specific cells.
NOTE: Please see (Xilinx Solution 4641) for information on how to instantiate the JTAG pins for general I/O in HDL.