UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
General Description:
In Slave Serial Mode Configuration of an xc4000XL device if the
CCLK starts out at a logic LOW, and is parked LOW after
configuration, the device may not configure. This was a known
problem with the xc3000 and xc4000 FPGA families, but was fixed
in the xc4000E family. However, some xc4000XL parts
exhibit this same problem.
Older FPGA familes had a maximum low time specification for
CCLK, `Tccl', however, this has not yet been characterized for
the xc4000XL. This has been fixed in the xc4000XLA devices
negating the characterization of a maximum Tccl.
Applications exhibiting this kind of behavior with xc4000XL
parts should be encouraged to invert the sense of the
configuration clock.
AR# 2841 | |
---|---|
日付 | 05/07/2014 |
ステータス | アーカイブ |
種類 | 一般 |