General Description: The problem described below may occur in QuickHDL when simulating a pre-synthesis functional (having instantiated RAM modules), post-synthesis functional, M1 post-synthesis functional, or post-route timing model (i.e., any simulation model that uses M1 VHDL/VITAL SimPrims).
RAMs may not simulate properly or respond to input stimuli under QuickHDL on HP Workstations. (Curiously, they simulate properly under other operating systems.) The information stored in a RAM may remain at its initial value, even after you have tried to write new data to the RAM.
Any pre-synthesis simulation will use the UniSim library, and any simulation after NGDBuild (post-synthesis functional or post-route timing simulation) will use the SimPrim library.
This problem is caused by a misinterpretation of the function called VitalStateTable by QuickHDL's VITAL-acceleration engine. To work around it, this function must be recompiled so that it is interpreted by the standard (non-VITAL) VHDL interpreter. This is done using the -novital switch in QVHCOM, e.g.:
If your VHDL UniSim or SimPrim library is not local or in a writeable directory, this command must be performed by your system administrator.
(NOTE: This can theoretically degrade the performance of the QuickHDL simulator, as the VitalStateTable function will no longer utilize VITAL acceleration. The extent of this performance degradation has not been quantified.)
For more information on compiling HDL models, please see (Xilinx Solution 2478). This problem will be fixed in QuickHDL version 8.5_5.0c.