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AR# 2865

FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow

説明

Keywords: FPGA, Design, Compiler, FPGA Compiler, Design Compiler, LogiBLOX, RAM,
instantiate, VHDL, Verilog

Urgency: standard

General Description:

How to instantiate LogiBLOX .ngc files in a VHDL or Verilog design, using FPGA Compiler.
The runscripts for the VHDL and Verilog examples are for FPGA Compiler. The same scripts
can be used for Design Compiler if the 'replace_fpga' command is removed.

For sample HDL code using LogiBLOX RAM and a corresponding run script, go to the
Xilinx Online Software Documentation:
http://www.xilinx.com/support/sw_manuals/1_5i/index.htm.
Under the Alliance Series group (in the left-hand pane), expand the "XSI Synopsys
Interface and Tutorial Guide" and select "Using LogiBLOX"

ソリューション

1

How to instantiate LogiBLOX in a FPGA Compiler VHDL design

Note: This example uses a LogiBLOX synchronous RAM. The procedure used can be
applied to instantiating any LogiBLOX.

(1) Open the LogiBLOX GUI and create a LogiBLOX memory. .ngo and .vhi files are created.

(2) Use the .ngo file name as the name of the 'component' instantiation in the VHDL code.
The .vhi file will contain the pin names and port map needed to instantiate the LogiBLOX memory.

(3) Place a 'dont_touch' on the instantiated LogiBLOX. If you have multiple instantiations of
LogiBLOX, place a 'dont_touch' on each of the instantiations.

(4) Synthesize the design. Note the example run script is no different from the normal FPGA
Compiler run script.

2

Verilog Code Example:

File1:


module test(address,dataout,datain,writen,clk);input [5:0] address;
output [3:0] dataout;
input [3:0] datain;
input writen;
input clk;
testram U0
( .A(address),
.DO(dataout),
.DI(datain),
.WR_EN(writen),
.WR_CLK(clk));
endmodule



File2:


module testram(A, DO, DI, WR_EN, WR_CLK);input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule




Verilog Runscript Example for a LogiBLOX Design:

read -f verilog "testram.v"
read -f verilog "test.v"

set_port_is_pad "*"
insert_pads

compile

replace_fpga

ungroup -all -flatten

write_script > test.dc

sh dc2ncf test.dc

remove_design testram

write -f xnf -h -o "test.sxnf"

3

How to instantiate LogiBLOX in a Synopsys Verilog Design

Note: This example uses a LogiBLOX synchronous RAM. The procedure used can be applied
to instantiating any LogiBLOX.

(1) Open the LogiBLOX GUI and create a LogiBLOX memory. .ngc and .vei files are created.

(2) Use the .ngc file name as the name of the 'module' instantiation in the Verilog code. The .vei
file will contain the pin names and port map needed to instantiate the LogiBLOX memory.

(3) In the .vei file, there is a 'module' description of the LogiBLOX. The module description
describes the pin names and pin directions. Place these lines in a seperate file and read them
into the Synopsys during the compile of the design. Create an empty Verilog file, which
contains only the LogiBLOX module name, pin names, and pin directions, for each type of
LogiBLOX instantiated in the Verilog code.

(4) Place a 'dont_touch' on the instantiated LogiBLOX. If you have multiple instantiations of
LogiBLOX, place a 'dont_touch' on each of the instantiations.

(5) Synthesize the design. Note the example run script is no different from the normal FPGA
Compiler runscript.

(6) Note, just before writing out the .sxnf or .sedif file, the LogiBLOX design is removed using
the 'remove_design' command. This prevents Synopsys from writing out an empty file for the
LogiBLOX design; if you are using LogiBLOX, you already have a .ngc file that represents the
LogiBLOX module. If Synopsys writes out an empty file for the LogiBLOX module, large
portions of your design could be deleted. A 'remove_design' must be done for every empty
Verilog file created from step (4) above.

4

VHDL Code Example:


library IEEE;
use IEEE.std_logic_1164.all;

entity test is
port (ADDRESS: IN std_logic_vector(5 downto 0);
DATAOUT: OUT std_logic_vector(3 downto 0);
DATAIN: IN std_logic_vector(3 downto 0);
WRITEN: IN std_logic;
CLK: IN std_logic);
end test;

architecture inside of test is
component testram
port (A: IN std_logic_vector(5 downto 0);
DO: OUT std_logic_vector(3 downto 0);
DI: IN std_logic_vector(3 downto 0);
WR_EN: IN std_logic;
WR_CLK: IN std_logic);
end component;

begin
U0: testram port map(A=>ADDRESS, DO=>DATAOUT, DI=>DATAIN,
WR_EN=>WRITEN, WR_CLK=>CLK);
end inside;



VHDL Runscript Example for a LogiBLOX Design:

analyze -f vhdl "test.vhd"
elaborate test

set_port_is_pad "*"
insert_pads

compile

replace_fpga

ungroup -all -flatten

write_script > test.dc

sh dc2ncf test.dc

write -f xnf -h -o "test.sxnf"
AR# 2865
作成日 09/26/1997
最終更新日 04/27/2007
ステータス アーカイブ
タイプ 一般