ERROR:baste:263 - The LOC constraint "BUFG_WNW, BUFGE_WNW, BUFGLS_WNW" (a BUFG location) is not valid for BUFGS symbol "<symbol name>" (output signal=<signal name>), which is being mapped to the following site types: BUFGLS
Cause: FPGA Express puts location constraints onto the global buffer instead of on the pad (EXT record). If you attempt to place a standard "Pxx" pin location constraint on a clock within Express, this error will occur.
This problem has been resolved with Express patch version 2.0.3. Please see (Xilinx Solution 3566) to download this patch.
ソリューション
1
Instead of using the pin number to constrain the clock, use the clock buffer name and location. Each XC4000EX/XL clock buffer is designated by a position name.
In FPGA Express: 1. Create an implementation. 2. Double click on the current Implemenation and select the Ports tab. 3. Under Pad Loc, replace the pin number with the GCK location name.
2
Another option is to place the pin location constraint in the UCF file using the following syntax: