We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 2966

XC2000/XC3000/XC4000/XC5200: Tying two output pins to enhance current drive



Special considerations must be taken into account when tying

two outputs to enhance drive capabilities.


Even though the two signals that are being tied come from the

same net, it is possible there maybe a few nanoseconds of

difference between the arrival of a signal in the two

pins. This means that for a few nanoseconds

there will be signal contention that may likely reduce

the life expectancy of the device.

The best way to reduce contention time to a fraction of

a nanosecond is to register the outputs using the output

flip flops inside the IOBs with a clock signal coming from a

global buffer. Or in the case of the 5200, use

the CLB flip flop in the slice that is right next to the IOB

that is going to be used so the direct lines can be used.
AR# 2966
日付 06/15/2011
ステータス アーカイブ
種類 一般