AR# 2977: SYNPLIFY: How to use the syn_useenables attribute?
AR# 2977
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SYNPLIFY: How to use the syn_useenables attribute?
説明
Keywords: Synplify, Verilog, VHDL, syn_useenables
Urgency: Standard
General Description: How to use the syn_useenables attribute?
By default, Synplify the syn_useenables attribute is set to true. This attribute is used to generate register components with clock enable pins on them. If you do not want this, or the technology you are using does no support it, then you can disable this behavior.
ソリューション
1
Use the Attributes Pane of SCOPE and specify the syn_useenables attribute with a value of 0 (disabled) for the registers you do not want to have enable pins on.