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AR# 2977

SYNPLIFY: How to use the syn_useenables attribute?

説明

Keywords: Synplify, Verilog, VHDL, syn_useenables

Urgency: Standard

General Description:
How to use the syn_useenables attribute?

By default, Synplify the syn_useenables attribute is set to true.
This attribute is used to generate register components with clock
enable pins on them. If you do not want this, or the technology
you are using does no support it, then you can disable this behavior.

ソリューション

1

Use the Attributes Pane of SCOPE and specify the syn_useenables attribute
with a value of 0 (disabled) for the registers you do not want to have enable
pins on.

2

Verilog
-------

module dff (d_in, clk, rst, ce, q_out);
input [7:0] d_in;
input clk, rst, ce;
output [7:0] q_out;

reg [7:0] q_out /* synthesis syn_useenables = 0 */;

always @(posedge clk or posedge rst)
if (rst)
q_out <= 8'h0;
else
if (ce)
q_out <= d_in;

endmodule
AR# 2977
作成日 10/22/1997
最終更新日 04/24/2007
ステータス アーカイブ
タイプ 一般