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AR# 3040

3.1i CORE Generator - Sample COREGen .coe coefficient files for a PDA FIR filter, RAM and ROM.

説明

Keyword: COREGen, CORE Generator, ROM, RAM, FIR, Filter, PDA, SDA

Urgency: Standard

General Description:
The following are sample CORE Generator coefficient (.coe) files for FIR Filters, ROM, and RAM.

The sample COE files may also be found in your COREGen installation, under the coregen\wkg directory in your COREGen installation tree.

ソリューション

1

FIR Filter:

component_name=pdafir;
number_of_taps=8;
radix=16;
input_width=8;
coef_width=8;
output_width=20;
symmetry=true;
cascade=false;
trim_empty_roms=false;
signed_input_data=false;
coefdata=20,A,15,34;

Here is a brief explanation of the keywords in the Coefficient File:

Component_name: Declares the name of the component.

Number_of_taps: Specifies the number of taps.

Radix: Specifies the base of the coefficient. (Radix=10 indicates that the coefficients are in base 10 (decimal) format; Radix=16 indicates that the coefficient is in hexadecimal format.)

Input_width: Specifies the input width.

Coef_width: Specifies the output width.

Output_width: Specifies the output width.

Symmetry: Specifies the symmetry of the filter. ("TRUE" indicates that the filter coefficients are symmetrical, "FALSE" means they are asymmetrical.)

Cascade: Specifies whether the cascade capability of the filter is enabled.

Trim_empty_rom: Trims out unnecessary logic associated with ROM modules. This option can save some resources by trimming out unused logic; however, use of this option may reduce the maximum output bit width.

For more information, please refer to the specification sheets for the FIR filters.

2

Registered (Distributed) ROM:

Component_name=rom48x8;
Data_width=8;
Address_width=6;
Depth=48;
Radix=16;
Memdata=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,2
1,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,
42,43,44,45,46,47;

For more information, please refer to the online specification sheet for the Registered ROMs in CORE Generator.

3

Dual-Port and Single-Port (Distributed) RAM:

Component_name=dpram48x8;
Data_width=8;
Address_width=6;
Depth=48;
Radix=16;
Memdata=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,
25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47;


The "Memdata" field allows you to specify the initialization values for your CORE Generator RAM. The format of a COE file for a Single-Port RAM is the same as that for a Dual-Port RAM.

For more information, please refer to the CORE Generator spec sheet for Registered RAMs.
AR# 3040
作成日 11/05/1997
最終更新日 07/11/2001
ステータス アーカイブ
タイプ 一般