UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3055

M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is driving multiple outputs

説明

Keywords: 9500, CPLD, Hitop, trim, macro, vhdl, abel, hierarchy, fitter

Urgency: Standard

General Description:

If you have multiple pins being driven by the same signal
inside a macro, and those pins in turn, drive output pins in
the top level schematic, the CPLD fitter will trim away all but one net coming out of the macro. This is true for both
ABEL and VHDL macros.


ソリューション

The current workaround for this issue is to have the signal drive multiple nets outside of the macro instead of from inside
the macro.

In addition, add a buf to the signals which are being trimmed.
You would then have the macro pin going to a buf -> obuf -> opad
on the top level for the signal that was being trimmed.
AR# 3055
作成日 08/31/2007
最終更新日 10/06/2008
ステータス アーカイブ
タイプ 一般