We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 3064

M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL.


Keyword: M1.3, ABEL, OPTX, x4kdr.

Urgency: Hot

The design can not pass the translate stage due to the OPTX error. The error message is as follow: ERROR: x4kdr: 7 - Netcheck: More than one active source pin was found for signal <signal_name>. Please check to ensure that all signals only have one driver...


This problem may happen if you are using foundation F1.3 and have ABEL macros instantiated in the schematic. The solution to that is resumed in the following steps: Under Design click on IMPLEMENT--->Click on OPTION--->Click on EDIT TEMPLATE--->Under OPTIMIZATION select SPEED or AREA, then click on OK and reimplement.
If the instantiated macros were written in VHDL, please look at solution record 2993.
AR# 3064
日付 04/10/2000
ステータス アーカイブ
種類 一般