AR# 30647

説明

Virtex-5 GTX VCS verilog functional and timing simulation error out and do not complete. This affects only simulations using GTX. It does not affect simulations using Virtex-5 GTP or Virtex-4 GT11 simulations.

ソリューション

To fix this issue for functional simulation in the simulation/functional/simulate_vcs.sh, change the line: 

$Xilinx/virtex5/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v \ 

to: 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v \ 

To fix this issue for timing simulation in the simulation/timing/simulate_vcs.sh, change the line: 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTP_DUAL_SWIFT.v 

to: 

$Xilinx/smartmodel/lin/wrappers/vcsmxverilog/GTX_DUAL_SWIFT.v