AR# 30939

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LogiCORE Serial RapidIO v4.3 - Core LCSBA implementation removes 64 MB of possible addressing space

説明

The current implementation of the core compares bits [2:9] of the incoming address with the value stated in the LCSBA register. The problem is that bits [0:1] are ignored in this comparison which reduces the amount of addressable memory.  

 

The memory is divided into 16 MB blocks. With [0:1] being a don't care, the core is removing 64 MB of addressable memory.  

 

Test case ran: Using the tasks provided in the example testbench, the LCSBA was set to 00. 

IREQ_DATA(`FT_2, 4'b0100, 34'h0_0000_0058, 31); Address = 34'h0_0000_0058 

NOTE: The packet created with the task above was re-routed to the Maintanence port and should have been given the address. 

 

IREQ_DATA(`FT_2, 4'b0100, 34'h0_2000_0058, 31); Address = 34'h0_2000_0058 

NOTE: The packet created with the task above was not re-routed to the Maintanence port which is correct, since bits [2:9] = 8'h20. 

 

IREQ_DATA(`FT_2, 4'b0100, 34'h2_0000_0058, 31); Address = 34'h2_0000_0058 

NOTE: The packet above is the one in question. This packet should not have been re-routed to the Maintanence port because bits [0:1] = 2'h2. However, the core is ignoring these bits in the comparison and does send this packet to the incorrect port. As a result, you would see the following packets go to the maintanence port: 

 

IREQ_DATA(`FT_2, 4'b0100, 34'h0_0000_0058, 31); Address = 34'h0_0000_0058 

IREQ_DATA(`FT_2, 4'b0100, 34'h1_0000_0058, 31); Address = 34'h1_0000_0058 

IREQ_DATA(`FT_2, 4'b0100, 34'h2_0000_0058, 31); Address = 34'h2_0000_0058 

IREQ_DATA(`FT_2, 4'b0100, 34'h3_0000_0058, 31); Address = 34'h3_0000_0058 

 

The lower three packets should not be re-routed.

ソリューション

This issue will be fixed in SRIO v4.4 scheduled to be released at the end of June 2008.

AR# 30939
日付 05/22/2014
ステータス アーカイブ
種類 一般
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