AR# 3115: XC2000 - Considerations when migrating an XC2000 design to a newer device family
XC2000 - Considerations when migrating an XC2000 design to a newer device family
The following should be considered when attempting to migrate from an existing XC2000 device to a newer FPGA device.
Usually the easiest migration path from an XC2000 to a newer device family is just to print out all of the schematics and re-enter the design. If the original design was performed on a design entry tool which allows for an easy migration path to a newer existing design entry tool, then by all means this should be done. But many XC2000 designs were either created within Xilinx Design Editor (XDE) or an out-dated design entry tool.
The biggest XC2000 device was an XC2064, which stands for 64 CLBs (each containing 1 Function Generator and one FF). This means that such a design typically is not too large and design re-entry is typically not a major task.
During the design migration, the following should be considered:
1. XC2000s have asynchronous SET and RESET on each FF. None of our other FPGA devices have this feature. If this design happens to use an asynchronous set and reset, one must be converted to a synchronous signal.
2. Pin compatibility. If the design can stay in the same device package, most of the pinouts can be preserved, but it is possible that not all of the pinouts can remain unchanged.
3. If the design is originated from a schematic, the design is most likely originally created in pre-unified libraries. These must be interpreted into unified equivalents.
4. Asynchronous paths in the design's timing will change. This must be accounted for.
5. If the design uses external crystal, XC5200 and XC4000 do not have XTL1 and XTL2 crystal amplifier pins. It is suggested that a canned oscillator be used.
6. XC5200 and XC4000 do not have PWRDWN pins. If the design is using this, use the GTS signal instead.
7. A timing simulation is highly recommended after the design conversion, to ensure that functionality did not change and that the design will run properly at system clocking speeds.