AR# 31164


Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causes received TLP bit errors due to Expansion ROM work-around


v1.8, v1.7.1 Known Issue 

If the device capability MPS is set to 128 or 256 bytes, it might cause bits to be corrupted in the first and third DWORD of a received packet on the user interface.  


Why does this happen?


In v1.7.1, a fix was added to the Block Plus Wrapper to permanently disable the Expansion ROM BAR. 

Prior to v1.7.1, the Expansion ROM BAR was always turned on and could not be disabled. 

This caused problems with many platforms, since most users did not need the Expansion ROM BAR for their design. 


The fix added to disable the expansion ROM BAR can interfere with received TLPs if the device capability MPS is set to 128 or 256 bytes, because it changes the address ranges on the block RAMs used to store incoming data from the default range when the MPS is set to 512 bytes.

The work-around was designed with the default of 512 bytes and did not consider that the MPS might be lower. 


To fix this problem, users should not change the CORE Generator GUI settings for the MPS request size to be lower than 512 bytes. 

This is the MPS value that will be contained in the Device Capability Register.

There is a potential problem with this work-around that the user might need to address. 

If the MPS capability is set to 512 bytes, on some higher end systems, the host might set the MPS of the device to be 512 bytes in the device command register (assuming the user application can handle TLPs up to this size).

Normally, the user application will base TLP packet size on the cfg_dcommand[7:5] output which tells the user application the MPS size programmed in the device command register. 

Keep in mind that if your user application cannot handle transfers of up to 512 bytes, the user logic needs to ensure it is aware that the value on cfg_dcommand[7:5] might be more than 128 bytes and act accordingly.

Even though the MPS could be set to 256 or 512 bytes due to this work around, the system should not be transmitting large Memory Write or Read packets downstream.

Large data transfers are always done by the endpoint through a bus master DMA type design. 


Revision History 


06/18/2008 - Initial Release

AR# 31164
日付 06/10/2015
ステータス アクティブ
種類 一般
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