# The purpose of this script is to resolve a simulation issue that occurs when # using the VHDL x8 pcie_blk_plus core in conjunction with the x4 downstream # port that is provided along with the example testbench. This script hacks the # x8 endpoint_blk_plus_v1_8fx.vhd core netlist and turns off SIM_RECEIVER_DETECT_PASS0(1) # for the four upper lanes (GTX4 and GTX6). This is required so that the x4 # downstream port will correctly simulate in conjunction with the x8 core. This # script is only being used for the x8 core configuration and only for the VHDL # flow. The output of this file is <core name>..vhd. The original # source file <core name>..vhd is left unchanged. Customers who intend to # simulate the x8 VHDL pcie_blk_plus core with their own x8 downtream port should use the # original source file <core name>.vhd and should not use this script to generate # a modified core netlist.