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AR# 31751

10.1 Timing Analyzer, Spartan-3A, 3A DSP, or 3AN - A warning about the minimum period for the clk0 output of the DCM period being too small is issued


When using the clk_out of a DCM on a Spartan-3A, 3A DSP, 3AN, I receive the following message about the output of my DCM: 


"WARNING:Timing:3328 - Timing Constraint "TS_AD9271_DCO_n = PERIOD TIMEGRP "AD9271_DCO_n" 3.99 ns HIGH 50%;" fails the minimum period check for the output clock sig_CLK0_DCM from DCM DCM_SP_DCO because the period constraint value (3990 ps) is less than the minimum internal period limit of 4166 ps. Please increase the period of the constraint to remove this timing failure." 


When I look in the data sheet for this device, the maximum output frequency for the output of the DCM with the clk_out output, the maximum frequency is 250 MHz. 


Why is this warning issued?


This warning can be ignored as long as you are running below 250 MHz. The analysis of the design will still be performed at the 250 MHz constraint. The software is incorrectly reporting 240 MHz for this value. The numbers that are listed in the data sheet are correct.

AR# 31751
日付 05/23/2014
ステータス アーカイブ
種類 一般