ソリューション
| (Xilinx Answer 33867) | Design Advisories for MVI (Multimedia, Video, and Imaging) IP including, but not limited to Image Processing Pipeline, Video On-Screen Display, Video DMA, Video Scaler, Video Timing Controller |
| (Xilinx Answer 35262) | How do I create scaling coefficients and COE files for the LogiCORE IP Video Scaler? |
| (Xilinx Answer 34828) | How do I simulate my Video IP pcore in EDK? |
General LogiCORE IP Video Scaler Issues:
LogiCORE IP Video Scaler v7.01.a
There is an ISE Design Suite and EDK v7.01.a Rev3 patch available in (Xilinx Answer 55898).
This patch was intended to fix issues listed below as (Xilinx Answer 55897), (Xilinx Answer 56043), (Xilinx Answer 56484) and (Xilinx Answer 57048)
There is a Software Driver v4.03.a patch available in (Xilinx Answer 55984).
This patch was intended to fix issues listed below as (Xilinx Answer 55985), (Xilinx Answer 55987), and (Xilinx Answer 56164).
- Initial release in ISE 14.3 and Vivado 2012.3 tools
Supported Devices (ISE) - All 7 series
- All Virtex-6
- All Spartan-6
Supported Devices (Vivado) New Features - Fixed clock domain issues with registers in the AXI4-Lite connection
Resolved Issues (ISE) Resolved Issues (Vivado) | (Xilinx Answer 47523) | Why do the AXI4-Lite register readbacks fail sometimes in simulation? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51232) | Why does my software hang when using the Video Scaler pcore driver in EDK? |
Known Issues (ISE) | (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52285) | Why do the INTC_IF interface register and pins not behave according to the documentation? |
| (Xilinx Answer 52289) | Why is an interrupt not generated when one of the error bits in the Status register are set? |
| (Xilinx Answer 52392) | Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected? |
| (Xilinx Answer 52664) | Why does an EOL error occur on the INTC_IF or in the interrupt registers, even when my frame size is valid? |
| (Xilinx Answer 52987) | Software Driver v4.01.aWhy doesn't SDK 14.3 fail to find the Video Scaler Driver v4.01.a? |
| (Xilinx Answer 52998) | Why does my s_axis_video_aclk and m_axis_video_aclk inputs get tied to ground in XPS if I do not connect them to my video clock? |
| (Xilinx Answer 55897) | Why does the output of the scaler wrap when the aperture includes the last pixel of the input frame? |
| (Xilinx Answer 55985) | Why does SDK fail to find the Video Scaler Software Driver v4.02.a when using the Video Scaler v7.01.a? |
| (Xilinx Answer 55987) | Why does SDK fail to compile the Video Scaler Software Driver v4.02.a when using IDS 14.5 or Vivado 2013.1? |
| (Xilinx Answer 56043) | Software reset does not work |
| (Xilinx Answer 56164) | Why does the Video Scaler stop accepting input video if the input, output and aperture are 2048 or larger and using the Video Scaler software driver? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
| (Xilinx Answer 56484) | Why does the writing of the coefficients sometimes fail after installing the patch for (Xilinx Answer 55980) | ? |
| (Xilinx Answer 57266) | Why am I unable to connect up the s_axis_video_aresetn and m_axis_video_aresetn signals from the XPS GUI? |
| (Xilinx Answer 57048) | Why do I see what appears to be random glitches or flickering for several frames each second, in video output from the Video Scaler? |
| (Xilinx Answer 61066) | Why is the m_axis_tvalid output always low? |
Known Issues (Vivado) | (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52285) | Why do the INTC_IF interface register and pins not behave according to the documentation? |
| (Xilinx Answer 52289) | Why does writing to the Status Register fail to clear the Error bits? |
| (Xilinx Answer 52392) | Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected? |
| (Xilinx Answer 52664) | Why does an EOL error occur on the INTC_IF or in the interrupt registers, even when my frame size is valid? |
| (Xilinx Answer 52987) | Software Driver v4.01.aWhy does SDK 14.3 fail to find the Video Scaler Driver v4.01.a? |
| (Xilinx Answer 55897) | Why does the output of the Scaler wrap when the aperture includes the last pixel of the input frame? |
| (Xilinx Answer 56043) | Software reset does not work |
| (Xilinx Answer 56164) | Why does the Video Scaler stop accepting input video if the input, output and aperture are 2048 or larger and using the Video Scaler software driver? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
| (Xilinx Answer 56484) | Why does the writing of the coefficients sometimes fail after installing the patch for (Xilinx Answer 55980) | ? |
| (Xilinx Answer 57048) | Why do I see what appears to be random glitches or flickering for several frames each second, in video output from the Video Scaler? |
| (Xilinx Answer 61066) | Why is the m_axis_tvalid output always low? |
LogiCORE IP Video Scaler v7.00.a - Initial release in ISE 14.2 and Vivado 2012.2 tools
Supported Devices (ISE) - All 7 series
- All Virtex-6
- All Spartan-6
Supported Devices (Vivado) New Features - Inclusion of AXI4Lite clock and reset.
- AXI4Lite - Other domain CDC now to be handled in the core, not the interconnect
Resolved Issues (ISE)
Resolved Issues (Vivado) Known Issues (ISE) Known Issues (Vivado) | (Xilinx Answer 47523) | Why do the AXI4-Lite register readbacks fail sometimes in simulation? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51232) | Why does my software hang when using the Video Scaler pcore driver in EDK? |
| (Xilinx Answer 52285) | Why do the INTC_IF interface register and pins not behave according to the documentation? |
| (Xilinx Answer 52289) | Why does writing to the Status Register fail to clear the Error bits? |
| (Xilinx Answer 52392) | Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected? |
| (Xilinx Answer 52664) | Why does an EOL error occur on the INTC_IF or in the interrupt registers, even when my frame size is valid? |
| (Xilinx Answer 55897) | Why does the output of the Scaler wrap when the aperture includes the last pixel of the input frame? |
| (Xilinx Answer 56043) | Software reset does not work |
| (Xilinx Answer 61066) | Why is the m_axis_tvalid output always low? |
LogiCORE IP Video Scaler v6.00.a - Initial release in ISE 14.1 and Vivado 2012.1 tools
Supported Devices (ISE) - Virtex-7
- Kintex-7
- Artix-7
- Zynq-7000
- Virtex-6
- Spartan-6
Supported Devices (Vivado) - Virtex-7
- Kintex-7
- Artix-7
- Zynq-7000
New Features - ISE 14.1 tools support
- Virtex-7, Kintex-7, Artix-7 and Zynq device support
- AXI4-Stream interface support for the input and output interfaces
- AXI4-Lite bus interface support for the processor interface
Resolved Issues | (Xilinx Answer 32127) | Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
| (Xilinx Answer 38671) | Why does CORE Generator crash when I try to load my COE file? |
| (Xilinx Answer 45434) | Why is the frame_rst output signal not available in EDK, when using the pcore interface with Live mode input? |
| (Xilinx Answer 45438) | Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048? |
| (Xilinx Answer 46438) | Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler? |
| (Xilinx Answer 46488) | Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project? |
| (Xilinx Answer 47523) | Why do the AXI4-Lite register readbacks fail sometimes in simulation? |
Known Issues (ISE) Known Issues (Vivado)
LogiCORE IP Video Scaler v5.0
- Initial release in ISE Design Suite 13.3
Supported Devices - Virtex-7
- Virtex-7 XT (7vx485t)
- Virtex-7 -2L
- Kintex-7
- Kintex-7 -2
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
New Features - ISE 13.3 tools support
- Added AXI-Stream interfaces on I/O
Resolved Issues | (Xilinx Answer 41489) | Why does the Video Scaler always generate for 4 phases, when Constant mode is selected? |
| (Xilinx Answer 42509) | What are the valid values for the aperture_start_pixel and the aperture_end_pixel? |
| (Xilinx Answer 43079) | Why does the Video Scaler fail to complete the processing of an input frame larger than 2048 x 2048? |
| (Xilinx Answer 43080) | Why is the Video Scaler constant mode GUI estimated frame rate slower than expected? |
| (Xilinx Answer 43582) | Why are the last few lines of my output video frame missing when upscaling? |
Known Issues | (Xilinx Answer 32127) | Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
| (Xilinx Answer 38671) | Why does CORE Generator crash when I try to load my COE file? |
| (Xilinx Answer 45434) | Why is the frame_rst output signal not available in EDK, when using the pcore interface with Live mode input? |
| (Xilinx Answer 45438) | Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048? |
| (Xilinx Answer 46438) | Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler? |
| (Xilinx Answer 46488) | Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project? |
| (Xilinx Answer 47523) | Why do the AXI4-Lite register readbacks fail sometimes in simulation? |
LogiCORE IP Video Scaler v4.0
- Release in ISE Design Suite 13.1
Supported Devices - Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/ LXT/SXT/FXT
- Spartan-3A DSP
New Features - Added AXI Lite interface to pcore, removing the PLB interface.
- Added Coefficient readback facility.
Resolved Issues | Fixed dual-engine 4:2:0 support. |
| (Xilinx Answer 40950) | Why is the Video Scaler so large when using the pcore interface? |
| (Xilinx Answer 40203) | When using the constant interface, why do I see ghosting in the horizontal direction, when downscaling an image larger than 720p? |
Known Issues | (Xilinx Answer 32127) | Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
| (Xilinx Answer 38671) | Why does CORE Generator crash when I try to load my COE file? |
| (Xilinx Answer 41489) | Why does the Video Scaler always generate for 4 phases, when Constant mode is selected? |
| (Xilinx Answer 42509) | What are the valid values for the aperture_start_pixel and the aperture_end_pixel? |
| (Xilinx Answer 43079) | Why does the Video Scaler fail to complete the processing of an input frame larger than 2048 x 2048? |
| (Xilinx Answer 43080) | Why is the Video Scaler constant mode GUI estimated frame rate slower than expected? |
| (Xilinx Answer 43582) | Why are the last few lines of my output video frame missing when upscaling? |
| (Xilinx Answer 45434) | Why is the frame_rst output signal not available in EDK, when using the pcore interface with Live mode input? |
| (Xilinx Answer 45438) | Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048? |
| (Xilinx Answer 46438) | Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler? |
| (Xilinx Answer 46488) | Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project? |
LogiCORE IP Video Scaler v3.0
- Release in ISE Design Suite 12.3
New Features - RGB/4:4:4 compatibility (previously YC 4:2:2 and YC4:2:0 only)
- 8, 10 and 12-bit compatibility (previously 8 bits only)
- Selection of single, dual or triple-engine implementations to increase throughput if required (previously only single-engine available)
- Spatial resolution up to 4096x4096 (previously up to 1920x1080)
- Shareable coefficients
- Full EDK GUI in addition to existing CORE Generator GUI (previously, EDK GUI was very rudimentary)
- Pre-loadable coefficients in Constant, GPP and EDK pcore modes (previously only in Constant mode)
- Core Version register added
- Sharper Upscaling coefficients in xscaler_coefs.c file for the pcore interface
Resolved Issues - Reversed order of coefficients in .coe file, to match the GPP interface
Known Issues | | Selection of Virtex-6 device, specifically the -3 speed-grade, causes the CORE Generator tool to error out |
| Video corruption in YC4:2:0 |
| (Xilinx Answer 32127) | Why do I receive X_ARAMB36 block RAM memory collisions when simulating the Video Scaler? |
| (Xilinx Answer 40950) | Why is the Video Scaler so large when using the pcore interface? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
| (Xilinx Answer 38671) | Why does the CORE Generator tool crash when I try to load my COE file? |
| (Xilinx Answer 40203) | When using the constant interface, why do I see ghosting in the horizontal direction, when downscaling an image larger than 720p? |
| (Xilinx Answer 41489) | Why does the Video Scaler always generate for four phases when Constant mode is selected? |
| (Xilinx Answer 42509) | What are the valid values for the aperture_start_pixel and the aperture_end_pixel? |
| (Xilinx Answer 43582) | Why are the last few lines of my output video frame missing when upscaling? |
| (Xilinx Answer 45434) | Why is the frame_rst output signal not available in EDK, when using the pcore interface with Live mode input? |
| (Xilinx Answer 46438) | Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler? |
LogiCORE IP Video Scaler v2.1 | Initial release in ISE Design Suite 12.1 |
New Features | (Xilinx Answer 33948) | Why is the frame_rstG (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs? |
Resolved Issues | (Xilinx Answer 33791) | Why does the Video Scaler pcore stop working after about 4-8 hours of operation? |
| (Xilinx Answer 33790) | Why do I receive an XST Compiler:410 error when I target a Virtex-6 or Spartan-6 device using the pCore interface? |
| (Xilinx Answer 33868) | Why do I not see any output when using the Video Scaler with a Memory Data Source and an Aperture Start Line of zero "0"? |
| (Xilinx Answer 34202) | Why are the results wrong when using a core clock greater than 2x the input clock rate? |
| (Xilinx Answer 33397) | Why does Constraint Interface limit my Aperture Start Pixel and Aperture End Pixel to 720p dimensions? |
| (Xilinx Answer 34253) | Why does the Video Scaler Input FIFO appear to skip some lines? |
| (Xilinx Answer 33398) | Why do I receive a warning about a missing top level when I generate the EDK Pcore interface? |
| (Xilinx Answer 34479) | Why does my pcore not have the parameters that I selected in the CORE Generator software? |
| (Xilinx Answer 34435) | How do input 4:2:0 chroma data when using a Memory Data Source? |
| (Xilinx Answer 35382) | Virtex-6 and Spartan-6 core should not be used in production due to potential block RAM memory related problems |
Known Issues | (Xilinx Answer 32127) | Why do I receive X_ARAMB36 block RAM memory collisions when simulating the Video Scaler? |
| (Xilinx Answer 35638) | Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 devices? |
| (Xilinx Answer 35460) | Why does frame_done not assert when I use the Video Scaler in 4:2:0 mode? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
LogiCORE IP Video Scaler v2.0
Important Note: This version of the Video Scaler should not be used to target Virtex-6 or Spartan-6 devices; see (Xilinx Answer 35382).
There was a v2.0 rev2 patch available in (Xilinx Answer 33393).
This patch was intended to fix issues listed below in (Xilinx Answer 33790) and (Xilinx Answer 33791).
- Initial release in ISE Design Suite 11.3
New Features - Support for Spartan-3A DSP-4 FPGA
- Support for Spartan-6 FPGA
- Support for Virtex-6 FPGA
- EDK pcore option can now be generated from the CORE Generator tool
- Constant (Fixed mode) option can now be generated from the CORE Generator software
- Video source can be either Live-feed or Memory-sourced
Resolved Issues - Timing closure now allows support for Spartan-3A DSP-4 FPGA
- (Xilinx Answer 32127) - Why do I have X_ARAMB36 block RAM memory collisions when simulating the Video Scaler v1.0?
Known Issues | (Xilinx Answer 33397) | Why does the Constraint Interface limit my Aperture Start Pixel and Aperture End Pixel to 720p dimensions? |
| (Xilinx Answer 33398) | Why do I receive a warning about a missing top level when I generate the EDK Pcore interface? |
| (Xilinx Answer 33790) | Why do I receive an XST Compiler:410 error when I target Virtex-6 or Spartan-6 devices using the pcore interface? |
| (Xilinx Answer 33791) | Why does the Video Scaler pcore stop working after about 4-8 hours of operation? |
| (Xilinx Answer 33868) | Why do I not see any output when using the Video Scaler with a Memory Data Source and an Aperture Start Line of zero (0)? |
| (Xilinx Answer 33948) | Why is the frame_rst (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs? |
| (Xilinx Answer 34202) | Why are the results wrong when using a core clock greater than 2x the input clock rate? |
| (Xilinx Answer 34253) | Why does the Video Scaler Input FIFO appear to skip some lines? |
| (Xilinx Answer 34435) | How do I input 4:2:0 chroma data when using a Memory Data Source? |
| (Xilinx Answer 34479) | Why does my pcore not have the parameters that I selected in the CORE Generator software? |
| (Xilinx Answer 35460) | Why does frame_done not assert when I use the video Scaler in 4:2:0 mode? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |
LogiCORE IP Video Scaler v1.0 - Initial release in ISE Design Suite 11.1
New Features Resolved Issues Known Issues | (Xilinx Answer 32127) | Why do I have X_ARAMB36 block RAM memory collisions when simulating the Video Scaler v1.0? |
| (Xilinx Answer 33948) | Why is the frame_rst (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs? |
| (Xilinx Answer 34202) | Why are the results wrong when using a core clock greater than 2x the input clock rate? |
| (Xilinx Answer 34253) | Why does the Video Scaler Input FIFO appear to skip some lines? |
| (Xilinx Answer 37094) | Why does intr_output_error assert unexpectedly at the beginning of my simulation? |