When instantiating a cell within HDL (VHDL or Verilog) to be compiled by FPGA Express, if a user inverts the signal in the port map, the pin is renamed in bus style. For example
STARTUP U1 (.GSR(!reset));
would give a pin named GSR<0>. This will cause connectivity problems with the instantiated block.
ソリューション
The workaround is to have an intermediate signal to invert the reset signal before the pin assignment. Example: