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AR# 3235

F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work

説明

Keywords: FPGA Express, 1.2, 2.0, instantiate, invert, <>

Urgency: Standard

When instantiating a cell within HDL (VHDL or Verilog) to be compiled by
FPGA Express, if a user inverts the signal in the port map, the pin is renamed
in bus style. For example

STARTUP U1 (.GSR(!reset));

would give a pin named GSR<0>. This will cause connectivity problems with the
instantiated block.

ソリューション

The workaround is to have an intermediate signal to invert the reset signal
before the pin assignment. Example:

foo = !reset;
STARTUP U1 (.GSR(foo));
AR# 3235
作成日 12/22/1997
最終更新日 03/19/2000
ステータス アーカイブ
タイプ 一般