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AR# 32398

11.1 EDK, xps_timer_v1_00_a - Registers are not initialized to '0' after core reset

説明

The following registers, Load registers, Load_Counter_Reg, Write_Load_Reg and others, are not set to '0' in the hardware after core reset. This is not according to the data sheet.

ソリューション

This issue has been fixed in the latest release of the xps_timer_v1_01_a core and is available in EDK 11.1. 

 

The EDK 11.1 will be available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 32398
日付 05/21/2014
ステータス アーカイブ
種類 一般
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