AR# 3245: M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
ERROR:x4kma:312 - The following symbols could not be constrained to a single CLB: RAM16X1S symbol "HREG_1/BANK2/DELTA/RAM1" (output signal=HREG_1/BANK2/DELTA/D0) FDCE symbol "HREG_1/BANK2/DELTA/FF1" (output signal=HREG_1/OUT2D0) The clock signals are of opposite polarity. These symbols share the same RLOC attribute value, which requires them to be mapped to the same CLB.
A fix for this merge problem is included in the current M1.4 Core Applications patch available from the Xilinx Download Area: