ERROR:Place:592 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
IOB / BUFGCTRL site pair. The clock IOB component <FPGA_CLK> is placed at site <H14>. The corresponding BUFG
component <U3_BUFG> is placed at site <BUFGCTRL_X0Y10> The clock IO site can use the fast path between the IO and the
Clock buffer if the IOB & BUFGCTRL are both placed in the same half of the device (TOP or BOTTOM). You may want to
analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may
use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design
to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It
is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "FPGA_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >
AR# 32531 | |
---|---|
日付 | 09/11/2014 |
ステータス | アクティブ |
種類 | 一般 |
デバイス | |
ツール |