AR# 32645


CPRI v2.1 - Virtex-5 FXT - Missing constraint in Example Design UCF


When when you generate a core for Virtex-5 FXT, there is a period constraint missing in the example design UCF.


The following constraint should be added to the ucf file: 


TIMESPEC "TS_recclk" = PERIOD "recclk_int" 153.6 MHz; 


This belongs below the line: 

NET "recclk_int" TNM_NET = "recclk_int";

AR# 32645
日付 05/21/2014
ステータス アーカイブ
種類 一般
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