AR# 32645

説明

When when you generate a core for Virtex-5 FXT, there is a period constraint missing in the example design UCF.

ソリューション

The following constraint should be added to the ucf file: 

TIMESPEC "TS_recclk" = PERIOD "recclk_int" 153.6 MHz; 

This belongs below the line: 

NET "recclk_int" TNM_NET = "recclk_int";