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AR# 32754

LogiCORE IP Video Timing Controller - Release Notes and Known Issues

説明

This answer record contains the Release Notes and Known Issues for the CORE Generator tools and LogiCORE IP Video Timing Controller. 

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues


Video Timing Controller Core Page:

https://www.xilinx.com/products/intellectual-property/ef-di-vid-timing.html

ソリューション

General LogiCORE IP Video Timing Controller Issues

(Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?
(Xilinx Answer 39413) What signals are needed for the timing to be correctly detected and regenerated?
(Xilinx Answer 47158) Why do I not see blanking signals generated when I select the blanking signal detection?

LogiCORE IP Video Timing Controller v5.01.a

There is a v5.01.a Rev3 patch available in (Xilinx Answer 52846)

This patch was intended to fix issues listed below as (Xilinx Answer 52724), (Xilinx Answer 54610), (Xilinx Answer 54611) and (Xilinx Answer 55980).

  • Initial Release in ISE Design Suite 14.3, Vivado Design Suite 2012.3

Supported Devices (ISE)

  • All 7 Series Devices
  • All Virtex-6 Devices
  • All Spartan-6 Devices

Supported Devices (Vivado)

  • All 7 Series Devices
New Features
  • Added Clock Domain Crossing Constraints

Bug Fixes

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?

Known Issues (ISE)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
(Xilinx Answer 52666) Software Driver v3.00.a - Why did the software the software driver only ever see one instance of the Video Timing Controller when using SDK in 2013.3/14.3?
(Xilinx Answer 52724) Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled?
(Xilinx Answer 52741) Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used?
(Xilinx Answer 54610) Why do I get an NGD Build error when using the VTC v5.01.a in 14.3 IDS EDK?
(Xilinx Answer 54611) Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled?
(Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?

Known Issues (Vivado)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
(Xilinx Answer 52666) Software Driver v3.00.a - Why did the software the software driver only ever see one instance of the Video Timing Controller when using SDK in 2013.3/14.3?
(Xilinx Answer 52724) Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled?
(Xilinx Answer 52741) Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used?
(Xilinx Answer 54611) Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled?
(Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?


LogiCORE IP Video Timing Controller v5.00.a

  • Initial Release in ISE Design Suite 14.2, Vivado Design Suite 2012.2

Supported Devices (ISE)

  • All 7 Series Devices
  • All Virtex-6 Devices
  • All Spartan-6 Devices

Supported Devices (Vivado)

  • All 7 Series Devices

New Features

  • Added AXI4-Lite Clock Domain
  • Updated interrupt enables to trigger multiple interrupts

Bug Fixes

(Xilinx Answer 51847) Why do I get an error about the component not being found, when trying to simulate the Video Timing Controller v4.00.a?

Known Issues (ISE)

(Xilinx Answer 52724) Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled?

Known Issues (Vivado)

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 52724) Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled?

LogiCORE IP Video Timing Controller v4.00.a

  • Initial Release in ISE Design Suite 14.1, Vivado Design Suite 2012.1

Supported Devices (ISE)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6

Supported Devices (Vivado)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000

New Features

  • ISE 14.1 design tools support
  • Virtex-7, Kintex-7, Artix-7, and Zynq device support
  • AXI4-Lite bus interface support for the processor interface

Bug Fixes

  • N/A

Known Issues

(Xilinx Answer 51249) Software Driver v2.00.a - Why did the software driver stop working with my Video Timing Controller core after updating to the latest version of the ISE Design Suite?
(Xilinx Answer 51847) Why do I get an error about the component not being found, when trying to simulate the Video Timing Controller v4.00.a?


LogiCORE IP Video Timing Controller v3.0

  • Initial Release in ISE 13.2 design tools
Supported Devices

(*)To access these devices in the ISE Design Suite, contact your Xilinx FAE.
  • Zynq-7000*
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA LX/LXT
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
  • Spartan-6 -1L XQ LX
  • Virtex-5 XC LX/LXT/SXT/TXT/FXT
  • Virtex-5 XQ LX/LXT/SXT/FXT
  • Spartan-3A DSP

New Features

  • Replaced PLB processor interface with AXI4-Lite interface.

Bug Fixes

  • Moved Interrupt Controller to Address offset 0x200 instead of 0x100 for pCore
  • Detection Status Registers readable in pCore
  • Added "OPTION USAGE_LEVEL = BASE_USER" to pCore MPD file
  • Resolved detection interrupt issues
  • (Xilinx Answer 38546) Why are the number of lines per frame being incorrectly detected?

Known Issues

(Xilinx Answer 50241) Why do I receive a BRESP error when trying to perform a soft reset using the command 0xA0000000 as recommended by the documentation?


LogiCORE IP Video Timing Controller v2.1


  • Initial release in ISE 11.4 design tools
New Features
  • Support for Generating Blanks from Syncs
  • Support for Detecting Video Formats without blanks (sync/active_video) only

Bug Fixes

  • Moved Interrupt Controller to Address offset 0x200 instead of 0x100 for pCore

Detection Status Registers readable in pCore Added "OPTION USAGE_LEVEL = BASE_USER" to pCore MPD file Resolved detection interrupt issues

(Xilinx Answer 35436) Why am I having problems reading the Interrupt Status Registers?
(Xilinx Answer 33829) Why are the detection ports still in the VHO file, when I did not select them in the core generation GUI?
(Xilinx Answer 33830) Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame?
(Xilinx Answer 35039) Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6 devices?
(Xilinx Answer 38729) Why does the Video Timing Controller pCore fail to generate in EDK with an XST error?

Known Issues

(Xilinx Answer 38545) Why is the Video Timing Controller so large when using the pCore interface?
(Xilinx Answer 38546) Why are the number of lines per frame being incorrectly detected?

LogiCORE IP Video Timing Controller v2.0

  • Initial release in ISE 11.4 design tools

New Features

  • Support for Spartan-6 FPGA
  • Support for Virtex-6 FPGA
  • EDK pCore option can now be generated from the CORE Generator tool

Bug Fixes

(Xilinx Answer 32913) Why do some Max Lines Per Frame values cause an "XST failed for v_timebase_v1_0" error during generation?

Known Issues

(Xilinx Answer 33829) Why are the detection ports still in the VHO file, when I did not select them in the core generation GUI?
(Xilinx Answer 33830) Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame?
(Xilinx Answer 35436) Why am I having problems reading the Interrupt Status Registers?
(Xilinx Answer 35039) Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6 FPGA?
(Xilinx Answer 38729) Why does the Video Timing Controller pCore fail to generate in EDK with an XST error?

LogiCORE IP Video Timing Controller v1.0

  • Initial release in ISE 11.2 design tools

New Features

  • Support for video frame sizes up to 4096 x 4096
  • Direct regeneration of output timing signals with independent timing and polarity inversion
  • Automatic detection and generation of horizontal and vertical video timing signals
  • Support for multiple combinations of blanking or synchronization signals
  • Automatic detection of input video control signal polarities
  • Programmable output video signal polarities
  • Generation of up to 16 additional independent output frame synchronization signals
  • High number of interrupts and status registers for easy system control and integration

Bug Fixes

  • N/A

Known Issues

(Xilinx Answer 32913) Why do some Max Lines Per Frame values cause a "XST failed for v_timebase_v1_0." error during generation?

アンサー レコード リファレンス

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
47158 LogiCORE IP Video Timing Controller - ブランク信号検出を選択してもブランク信号が生成されない N/A N/A
39413 LogiCORE IP Video Timing Controller - タイミングを正しく検出し生成するために必要な信号 N/A N/A
38729 LogiCORE IP Video Timing Controller v2.0 - XST エラーが発生すると Video Timing Controller pCore が EDK で生成できない N/A N/A
35436 LogiCORE IP Video Timing Controller v2.0 - 割り込みステータス レジスタを読み出すことができない N/A N/A
35039 LogiCORE IP Video Timing Controller v2.0 - Spartan-6 または Virtex-6 をターゲットにしている場合、垂直タイミングの取り込み値が間違っている、またはステータス レジスタがアップデートされない N/A N/A
33830 LogiCORE IP Video Timing Controller v2.0 - Mismatch between the behavioral simulation and the post-implementation gate level simulation results when using the default GUI values for Max Clock Per Line and the Max Lines Per Frame N/A N/A
33829 LogiCORE IP Video Timing Controller - Why are the detection ports still in the VHO file when I did not select them in the core generation GUI? N/A N/A
38545 LogiCORE IP Video Timing Controller - pCore インターフェイスを使用すると Video Timing Controller が非常に大きくなる N/A N/A
38546 LogiCORE IP Video Timing Controller - フレームごとのライン数が間違って検出される N/A N/A
50241 LogiCORE IP Video Timing Controller v3.0 - 資料にあるようにコマンド 0xA0000000 を使用してソフト リセットを実行しようとするとスレーブ応答 (BRESP) エラーが発生する N/A N/A
51483 ISE 14.2 / Vivado 2012.2 Video IP - ビデオ入力から AXI-4 Stream 入力コアにパーシャル入力フレームを送信すると、ビデオ IP がフリーズする N/A N/A
51847 LogiCORE IP Video Timing Controller v4.00.a - シミュレーションしようとするとコンポーネントが見つからないというエラー メッセージが表示される N/A N/A
52215 14.3/2012.2 ビデオ IP - コアのタイミングが満たされず、クリティカル警告が表示される N/A N/A
52666 LogiCORE IP Video Timing Controller、Software Driver v3.00.a - 2013.3/14.3 で SDK を使用するとソフトウェア ドライバーで Video Timing Controller のインスタンスが 1 つしか認識されない N/A N/A
52724 LogiCORE IP Video Timing Controller (VTC) v5.01.a - VTC の生成および検出の両方が有効な場合、VTC 生成は常に VTC 検出がロックするまで待機する N/A N/A
52741 Video Timing Controller (VTC) v5.01.a - AXI4-Lite インターフェイスを使用する場合、VTC の生成によって常にスタートアップに 720p の出力タイミング信号が作成される N/A N/A
52846 LogiCORE IP Video Timing Controller v5.01.a - Video Timing Controller のパッチ アップデート N/A N/A
54610 LogiCORE IP Video Timing Controller v5.01.a - 14.3 ISE Design Suite の EDK で VTC v5.01.a を使用すると、NGDBuild エラーが表示される N/A N/A
54611 LogiCORE IP Video Timing Controller v5.01.a - 検出と生成の両方がイネーブルの場合、Video Timing Controller Generator がブランキング信号に対して早くリセットされる N/A N/A
55980 LogiCORE Video Timing Controller v5.01.a - AXI4-Stream のクロック周波数と AXI4-Lite インターフェイスのクロック周波数が異なると、AXI4-Lite バスでの書き込みがエラーになる N/A N/A

関連アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
47158 LogiCORE IP Video Timing Controller - ブランク信号検出を選択してもブランク信号が生成されない N/A N/A
39413 LogiCORE IP Video Timing Controller - タイミングを正しく検出し生成するために必要な信号 N/A N/A
38729 LogiCORE IP Video Timing Controller v2.0 - XST エラーが発生すると Video Timing Controller pCore が EDK で生成できない N/A N/A
38546 LogiCORE IP Video Timing Controller - フレームごとのライン数が間違って検出される N/A N/A
38545 LogiCORE IP Video Timing Controller - pCore インターフェイスを使用すると Video Timing Controller が非常に大きくなる N/A N/A
35436 LogiCORE IP Video Timing Controller v2.0 - 割り込みステータス レジスタを読み出すことができない N/A N/A
35039 LogiCORE IP Video Timing Controller v2.0 - Spartan-6 または Virtex-6 をターゲットにしている場合、垂直タイミングの取り込み値が間違っている、またはステータス レジスタがアップデートされない N/A N/A
33830 LogiCORE IP Video Timing Controller v2.0 - Mismatch between the behavioral simulation and the post-implementation gate level simulation results when using the default GUI values for Max Clock Per Line and the Max Lines Per Frame N/A N/A
33829 LogiCORE IP Video Timing Controller - Why are the detection ports still in the VHO file when I did not select them in the core generation GUI? N/A N/A
32913 LogiCORE Video Timing Controller v1.0 - Why do some Max Lines Per Frame values cause an "XST failed for v_timebase_v1_0" error during generation? N/A N/A
AR# 32754
日付 07/19/2018
ステータス アクティブ
種類 リリース ノート
IP
  • Video Timing Controller
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