"ERROR:HDLCompiler:40 - "<file>.vhd" Line xx: <name> is not a component"
Example Code:
File: ex_0001.vhd Compilation Library: work
library ieee; use ieee.std_logic_1164.all;
package my_pack_0001 is
component my_name is port(in_port : in std_logic; out_port: out std_logic); end component;
end package;
-----------------------------------
library ieee; use ieee.std_logic_1164.all; library work; use work.my_pack_0001.all;
entity ex_0001 is port(in_port : in std_logic; out_port: out std_logic); end ex_0001;
architecture beh of ex_0001 is signal my_name : std_logic; begin my_name <= in_port; my_inst : my_name port map(in_port =>my_name, -- Note: Error points here out_port=>out_port); end;
component my_name is port(in_port : in std_logic; out_port: out std_logic); end component;
end package;
-----------------------------------
library ieee; use ieee.std_logic_1164.all; library work; use work.my_pack_0001.all;
entity ex_0001 is port(in_port : in std_logic; out_port: out std_logic); end ex_0001;
architecture beh of ex_0001 is signal my_name : std_logic; begin my_name <= in_port; my_inst : my_name port map(in_port =>my_name, -- Note: Error points here out_port=>out_port); end;