ERROR:HDLCompiler:940 - " ex_0005.vhd" Line 16: Unmatched pragma translate/synthesis_off pragma found. A matched pair of translate_off and translate_on directives with same keywords is required.
VHDL サンプル コード
library ieee; use ieee.std_logic_1164.all;
entity ex_0005 is port(clk: in std_logic; d : in std_logic; q : out std_logic); end ex_0005;
architecture beh of ex_0005 is begin process (clk) begin if (clk'event and clk='1') then q <= d; -- pragma translate_off q <= not (d); -- translate_on end if; end process; end;
entity ex_0005 is port(clk: in std_logic; d : in std_logic; q : out std_logic); end ex_0005;
architecture beh of ex_0005 is begin process (clk) begin if (clk'event and clk='1') then q <= d; -- pragma translate_off -- Note: Error points here q <= not (d); -- pragma translate_on end if; end process; end;
File: ex_0005_v.v Compilation Library: work
module ex_0005_v (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) begin q <= d; // pragma translate_off -- Note: Error points here q <= not (d); // pragma translate_on end