ERROR:HDLCompiler:637 - "<file>.vhd" Line xx: Net state[7] is constantly driven from multiple places ERROR:HDLCompiler:208 - "<file>.vhd" Line yy: Another driver from here
コード例 :
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity ex_0008 is port(clk,reset : in std_logic; output : out std_logic_vector(7 downto 0) ); end ex_0008;
architecture bhv of ex_0008 is signal state : std_logic_vector(7 downto 0); begin process( reset , clk ) begin if(reset = '1') then output <= "00000000"; state <= "00000000"; elsif(clk'event and clk = '1') then case state is when "00000000" => output <= "00000001"; state <= "00000001"; when "00000001" => output <= "00000010"; state <= "00000010"; when "00000010" => output <= "00000011"; state <= "00000011"; when others => output <= "00000100"; state <= "00000000"; end case; end if; end process;