ERROR:HDLCompiler:56 - <file>.vhd Line xx: <name> is not a signal.
このコード名では、ポートとプロセスの名前が両方とも q のためにエラー メッセージが表示されます。
library ieee; use ieee.std_logic_1164.all;
entity ex_0004 is port(clk: in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end ex_0004;
architecture beh of ex_0004 is begin genloop: for i in 0 to 3 generate q: process (clk) begin if (clk'event and clk='1') then q <= d; -- Note: Error points here end if; end process; end generate; end;
entity ex_0004 is port(clk: in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end ex_0004;
architecture beh of ex_0004 is begin genloop: for i in 0 to 3 generate q_label: process (clk) begin if (clk'event and clk='1') then q <= d; -- Note: Error points here end if; end process; end generate; end;