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AR# 3301

FPGA Express 2.0/Foundation 1.4: Creating HDL Macros with FPGA Express 2.0 for Placement on a Foundation 1.4 Top-Level Schematic


Keywords: macro, HDL, Verilog, VHDL, FPGA Express, Foundation, 1.4, 2.0

Urgency: Standard

General Description:

FPGA Express 2.0 can be used as a module generator. An HDL design can be
synthesized with FPGA Express and the Express XNF can be placed in a
Foundation 1.4 schematic.

For this solution using Foundation 1.3 and FPGA Express 1.2,
see (Xilinx Solution 3013).


(1) Create the Foundation Project

The Foundation project should be created first. If the project has not yet
been created, select File->New Project (in the Foundation Project Manager) and
choose the appropriate device family and specify a project name. For more
information on creating and working with Foundation projects, refer to the the
Foundation F1.4 Quickstart Guide and Online Help.

(2) Compile the HDL Code in FPGA Express

Create a project in FPGA Express, if the project does not already exist, and
synthesize the HDL design as described in the FPGA Express documentation.
When performing the 'Create Implementation' step, be sure that the 'Do not
insert I/O pads' box is checked:

When performing the 'Export Netlist' step in FPGA Express, browse to the
Foundation project directory created above, and save the netlist into this

(3) Importing the Netlist into a Foundation Schematic

Open the Foundation project created in Step 1. To import the XNF from FPGA
Express into the Foundation schematic, select "Hierarchy->Create Macro Symbol
from Netlist" from the Schematic Editor. This will import the netlist into the
Foundation project, and create an associated symbol for placement on the

Connectivity between this symbol and the XNF file is done by name, so do not
change the name of one without changing the name of the other.

The symbol will be automatically be added to the Foundadtion project library.
To place the symbol on the schematic, brows the the 'SC Symbols' list of
library components to find the module. The name of the module will be the
same as the name of the imported XNF netlist.

(4) Simulate the Design

To functionally simulate the design, enter the Logic Simulator by clicking
the 'SIM Funct' button in the Foundation Project Manager. The design,
including the FPGA Express generated XNF netlist, will be loaded into the
simulator. To perform timing simulation, follow the Foundation procedures
for timing simulation as if the design were a pure schematic.

Note: The M1.4 core technology software, like Verilog, is case-sensitive with
respect to names. VHDL is not case-sensitive, but the XNF written out by FPGA
Express will follow the case-sensitivity used in the Verilog or VHDL code.
If case-sensitivity is not followed consitently when making constraints, the
M1.4 software may not be able to properly merge FPGA Express 2.0 XNF with EDN
files from Foundation 1.4.
AR# 3301
作成日 01/15/1998
最終更新日 08/19/1999
ステータス アーカイブ
タイプ 一般