-- This will work for XC5200, though the reset signal on the startup -- block is labeled GR. Synplify will map GSR signal name to GR in -- the netlist.
library IEEE; use IEEE.std_logic_1164.all; library xc4000; use xc4000.components.all;
entity use_gr is port ( reset : in STD_LOGIC ); end use_gr;
architecture xilinx of use_gr is
begin
-- the signal reset initializes all registers using the -- global STARTUP signal U1 : STARTUP port map (GSR => reset);
end xilinx;
2
// This will work for XC5200, though the reset signal on the startup // block is labeled GR. Synplify will map GSR signal name to GR in // the netlist.