AR# 3330: Foundation F1.3, FPGA Express: Functionality incorrect for Express modules on Schematics
Foundation F1.3, FPGA Express: Functionality incorrect for Express modules on Schematics
Keywords: Express, VHDL, Verilog, INV, simulate
General Description: A schematic design with Express XNF-based modules instantiated in it will functionally simulate fine, will be functionally incorrect in timing simulation or in the actual chip.
One possible cause of this problem is due to a bug with the EDIF netlister from the Foundation Schematic Editor. The problem is that when the XNF file from FPGA Express is "imported" into the Foundation Schematic Design, any INV pin properties which may exist in the XNF file are not properly translated into the EDIF file for the whole design. Thus, these INV properties are "lost" in the translation, the pins in question are no longer inverted, and the functionality of the design is therefore altered.
The workaround for this problem is to manually create the symbol for the XNF file, rather than "Importing" the netlist into the Schematic Editor. This way, the XNF file is treated like a true "black box" and therefore the INV properties are properly translated by NGDBUILD in the Translate phase of the Implementation flow. Follow these steps to create the symbol:
1. If the macro for the Express module has already been created by Importing the netlist, this macro must first be deleted. * Enter the Library Manager from the Tools menu in the Project Manager. * Locate the appropriate project library and double-click on it to display the project library macros. * Locate the Express macro, and highlight it, then select Object->Delete. Be sure that the Preserve Source Files box is checked. * Finally, delete the <macro>.ALR file, located in the project directory. This can be done through either the Windows Explorer or from a DOS Prompt. 2. To recreate the symbol, select Hierarchy->New Symbol Wizard from the Schematic Editor. 3. Enter the name for the macro. Use the same name as the XNF file from Express. 4. Choose 'Empty' for Contents of symbol. 5. Enter all the pins for the symbol in the Ports window. * Refer to either the XNF file or the VHDL file for the names of the pins. * IMPORTANT!! For bus pins, each pin must be listed individually. For example, if you have an 8 bit bus, instead of creating one pin called DATA[7:0], you must create 8 pins, called DATA<0>, DATA<1>, etc. This is due to a bug in the Foundation Schematic Editor. We are sorry for this inconvenience. 6. After the symbol creation is complete, place the symbol on the schematic sheet. 7. Add the following attribute to the symbol: $FILE=filename.xnf * To do this, double-click on the symbol, and in the Parameters section of the Symbol Properties window, type $FILE in the Name field, and <filename>.xnf in the Description field. (<filename> is the name of the XNF file from Express) Click Add.
For Functional Simulation, you must first go through the Translate step in the Design Manager Implementation. Then, return to the Foundation Project Manager and select Tools->Checkpoint Simulation. Choose the appropriate .NGD file.
**Note: This problem will be resolved in Foundation F1.4, and is independant of the version of Express used.