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AR# 33311

LogiCORE IP RXAUI v1.1 and v1.1 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5


This Answer Record contains the Release Notes for the LogiCORE IP RXAUI v1.1 Core, which was released in the 11.3 ISE software, and v1.1 rev1, which was released in the ISE 11.5 software.  This Answer Record includes the following: 

  • New Features 
  • Bug Fixes  
  • Known Issues 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:  http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf


New Features 

  • First Release of Core. 

Resolved Issues in v1.1 

  •  First Release of Core.  

Resolved Issues in v1.1 rev1 

  • (Xilinx Answer 33486) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers  
  • (Xilinx Answer 33488) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated 
  • (Xilinx Answer 33649) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition  
  • (Xilinx Answer 34160) - LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors

Known Issues in v1.1 rev1 

  • (Xilinx Answer 33489) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA Example Design 
  • (Xilinx Answer 33893) - LogiCORE RXAUI v1.1 - Implementing Virtex-6 FPGA Example Designs results in MAP errors for some device packages

アンサー レコード リファレンス

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
34160 LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors N/A N/A

関連アンサー レコード

AR# 33311
日付 05/23/2014
ステータス アーカイブ
種類 リリース ノート
デバイス 詳細 概略